A number of you have asked about running the data link at speeds greater than 2 Mbps. There are at least three issues related to doing this successfully.
The last IF bandwidth should be increased to accomodate the modulated signal. How wide this should be depends upon what is done in (2) but Carson's rule is probably a very good start: make sure that the L/C ratio is picked to result in low enough Q to pass 2*(deviation +rate). For example if you choose to deviate 2 MHz with 10 Mbps data, that will translate to a 3 dB bandwidth on the order of 2*(2+5)=14 MHz.
The discriminator also needs to be de-Q'd enough to give relatively linear output over the range of the deviation. Probably reducing the value of the shunt R across the quadrature tank is sufficient to accomplish this.
The answer to (2) depends upon how fast you want to go and which transceiver you decide to use. I found that the simplest door-opener transceivers which use a Gunn oscillator and do not have electronic tuning really are not suitable at 10 Mbps. They might be coaxed into working at half that speed but they simply don't have enough performance with low distortion at higher deviations to be able to do a good job at Ethernet speeds.
On the other hand, the electronically tuned varieties of transceivers like the Ma/Comm Gunnplexers, seem to be fine. If you have a pair of these you plan on using, see part II of my series in Ham Radio Magazine Designing a Station for the Microwave bands in the June 1988 issue, pages 31 and 32, for a plot of the tuning curve and for a suggested electronic tuning circuit. Microwave Station photo showing the original "transverter stack" The HF transceiver is to the left of the picture with the local oscillator assembly next to it. the 1296 MHz and 10368 MHz RF heads present are on the right side. Another View of it.
How to solve (3) is really out of my territory. If you are planning full Ethernet speed, perhaps you can simply use an Ethernet card. Whether or not there are any problems over long paths, where the propagation delay might cause troubles with the 802.3 protocol I don't really know for sure. N6RCE talked with Ethernet card and chipset designers who indicated that these cards couldn't be moved significantly away from 10 Mbps. I confess that I still don't understand how this can be since I don't see anything hardcoded into the silicon that can have the kind of precision it would take to "know" it was being asked to run at the wrong speed. Perhaps dynamic RAM or some of the gates might fail if run at 10% or less of design speed but I have trouble understanding what else would likely go wrong at, say, half speed.
On the other hand, perhaps there is a required relationship for many card implementation which expects the chipset clock and the host buss clock to be related in some fashion.
If someone spends time on this and discovers some answers, please indicate.
Other than Ethernet cards, in the amateur world there seems to be only Gracilis and Ottawa PI2 cards. I understand that the former might be expected to go at 1-2 Mbps and from my experience, I think the Ottawa cards might do .6 Mbps with internal clock recovery if 20M components and clock were substituted for the standard issue.
I hope that this might help some of you considering running the hardware at higher speeds.
73
Glenn n6gn
